This invention relates generally to semiconductor field effect power devices having insulated control gates, and more particularly, the invention relates to such devices which are readily integrable in semiconductor integrated circuits and methods of making the same.
Traditionally, power semiconductor devices with large current carrying capability have been fabricated with vertical current flow from one major surface of a semiconductor chip to an opposing major surface.
FIG. 1 is a section view of a prior art power MOSFET structure which uses double diffusion techniques to achieve very short, well-controlled channel lengths. Two N.sup.+ diffused regions 10 formed in respective P-doped diffused regions 12 form the source regions which are contacted by the contacts 14. A gate contact 16 is provided on gate insulation 18 over the channel regions in P regions 12. An N.sup.- epitaxial drift region 20 and an N.sup.+ substrate region 22 form the drain of the power MOSFET. A drain contact 24 is provided on an opposing surface of the chip in contact with the N.sup.+ region 22. Such a device is disclosed in U.S. Pat. No. 4,072,975, issued Feb. 7, 1978, for example.
FIG. 2 is a section view of a prior art insulated gate bipolar transistor (IGBT) which is very similar to the power MOSFET of FIG. 1, and like elements have the same reference numerals. However, the IGBT has a heavily doped P.sup.+ type region 24 which functions as an anode and forms a PN junction with the lightly-doped N.sup.- drift region 20. The P.sup.+ region replaces the N.sup.+ drain region 22 of the conventional power MOSFET illustrated in FIG. 1. Such a device is disclosed in U.S. Reissue Pat. No. 33,209 and in U.S. Pat. No. 4,364,073.
The vertical device designs of these prior art devices result in significant reduction in chip area compared to lateral devices and also minimize electric field crowding. Unfortunately, the placement of one large current carrying terminal on the back side of the chip, characteristic of vertical device designs, limits the circuit designer to one power device per chip. Lateral power devices, on the other hand, are not limited to one device per chip because all of their contacts are on the top surface. Lateral power devices are used in smart power applications where a number of power devices are integrated on the same chip with low power control and detection circuits. However, lateral devices generally possess very large drift regions resulting in inefficient utilization of chip area.
The present invention is directed to semiconductor field effect power devices such as the power MOSFET and the IGBT which are readily integrable in a semiconductor integrated circuit.